
`include "mux1x8_defs.v"

`timescale 1ns / 1ps

module mux1x8(
	i_sel,
	i_in0,
	i_in1,
	i_in2,
	i_in3,
	i_in4,
	i_in5,
	i_in6,
	i_in7,

	o_out
);

parameter DATA_WIDTH	= 1;

input [`MUX1X8_SEL_WIDTH-1:0] i_sel;

input [DATA_WIDTH-1:0]	i_in0;
input [DATA_WIDTH-1:0]	i_in1;
input [DATA_WIDTH-1:0]	i_in2;
input [DATA_WIDTH-1:0]	i_in3;

input [DATA_WIDTH-1:0]	i_in4;
input [DATA_WIDTH-1:0]	i_in5;
input [DATA_WIDTH-1:0]	i_in6;
input [DATA_WIDTH-1:0]	i_in7;

output [DATA_WIDTH-1:0]	o_out;
reg [DATA_WIDTH-1:0]	o_out;

always@( 	i_sel or i_in0 or i_in1 or i_in2 or i_in3 or 
					i_in4 or i_in5 or i_in6 or i_in7 )
begin
	case( i_sel )
		`MUX1X8_SEL_I0 :	o_out = i_in0;
		`MUX1X8_SEL_I1 :	o_out = i_in1;
		`MUX1X8_SEL_I2 :	o_out = i_in2;
		`MUX1X8_SEL_I3 :	o_out = i_in3;						
		`MUX1X8_SEL_I4 :	o_out = i_in4;
		`MUX1X8_SEL_I5 :	o_out = i_in5;
		`MUX1X8_SEL_I6 :	o_out = i_in6;			
		`MUX1X8_SEL_I7 :	o_out = i_in7;
	endcase
end

endmodule
